The level of device integration continues to rise and the performance requirements of power devices on integrated circuitry continue to be more demanding. As digital circuit components become more compact it is desirable to reduce overall size of lateral power devices. However, as feature sizes shrink it is difficult to maintain voltage operating ranges and tolerance to reverse bias conditions.
These issues are especially relevant to the consumer portable electronic market. Performance demands require a growing array of peripheral functions, most commonly including display drivers, RF interfacing, and battery operation. To meet ever increasing consumer demands the portable designs must perform energy management and power conversion functions with increased efficiency.
Power integrated circuitry such as used in portable power supplies typically incorporates high voltage transistors with low voltage circuitry to efficiently manage battery usage and energy conversion. Due to performance requirements of the power device (e.g., fast switching speed, low “on” resistance and low power consumption during switching operations) the power device of choice for many power integrated circuits is the Lateral Double Diffused MOS transistor (LDMOS). When compared to bipolar transistor devices the LDMOS can provide relatively low on-resistance and high breakdown voltage, However, with the drive to further reduce device sizes and improve operational efficiencies, there remain limited means for sustaining or improving these device characteristics.
Further reductions in on-resistance could be achieved by increasing the dopant level in the LDMOS conductivity path, e.g., the drift region, or by reducing the length of the drift region, but such approaches have trade-offs impacting other aspects of device performance. For example, the lower resistances which would be achievable with higher dopant concentrations can degrade device breakdown voltage characteristics. Reductions in the length of the drift region can result in higher field concentrations near the gate and also lead to lower breakdown voltages.
Because the consumer market of today demands integrated circuitry having the combination of increased device density and lower power consumption, e.g., to both extend battery life and reduce overall cost, the progression to finer line geometries presents a challenge to develop techniques to design around inherent limitations in device on-resistance and breakdown voltages. Generally, it is a desire in the art to improve the safe operating area of such devices while reducing power dissipation.